`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:53:02 10/20/2012
// Design Name:   pong_engine
// Module Name:   C:/Users/Maria Victoria/workspace/Pong/TestFMS.v
// Project Name:  Pong
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: pong_engine
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TestFMS;

	// Inputs
	reg clk_i;
	reg reset_sync;
	reg startGame;
	reg up_sync;
	reg down_sync;
	reg increase_Incrash;
	reg new_frame;

	// Outputs
	reg [5:0] ini_speed_x;
	reg [5:0] ini_speed_y;
	wire [9:0] ball_x;
	wire [9:0] ball_y;
	wire [9:0] paddle_y;
	wire gameOver;

	// Instantiate the Unit Under Test (UUT)
	Control_Unit uut (
		.clk_i(clk_i), 
		.reset_sync(reset_sync), 
		.startGame(startGame), 
		.up_sync(up_sync), 
		.down_sync(down_sync), 
		.increase_Incrash(increase_Incrash),  
		.ini_speed_x(ini_speed_x), 
		.ini_speed_y(ini_speed_y), 
		.ball_x(ball_x), 
		.ball_y(ball_y), 
		.paddle_y(paddle_y), 
		.gameOver(gameOver)
	);

	initial begin
		// Initialize Inputs
		clk_i = 0;
		reset_sync = 0;
		startGame = 0;
		up_sync = 0;
		down_sync = 0;
		increase_Incrash = 0;
		new_frame = 0;
		ini_speed_x=1;
		ini_speed_y=1;
		reset_sync=1;
		// Wait 100 ns for global reset to finish
		#100;
		reset_sync=0;
      startGame = 1;
		new_frame=1;
		// Add stimulus here

	end
    always #20 clk_i <= ~clk_i;      
endmodule

